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Computer Organization and Architecture: A Pedagogical Aspect

Indian Institute of Technology Guwahati via NPTEL

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Overview

Computer Organization and Architecture (COA) is a core course in the curricula of Computer Sciences as well as Electronics and Electrical Engineering disciplines at the second-year level in most of the Indian universities and technical institutions. This is the first course in COA and the course would provide students with an understanding of the design of fundamental blocks used for building a computer system and interfacing techniques of these blocks to achieve different configurations of an “entire computer system”.

This course will be developed and taught with respect to Objectives based on Bloom’s Taxonomy. First, we will highlight the main objectives the course is aimed to achieve. Following that, at each module, we will specify the module level objectives and demonstrate how these objectives meet the course level main goals in unison. At the leaf level i.e., the units, we will point the specific objectives of the lecture. Also, it will be demonstrated how the unit level objectives satisfy the parent module level objectives. Further, each module will have a module level problem which needs concepts of all the units therein to solve. Finally, a comprehensive course level problem related to design of “entire computer system” will be discussed which meets all the course level objectives.

Syllabus

Module 1: Basics: Functional Blocks in a Computer System, Number system and Computer Arithmetic (Week 1)

Basic functional blocks of a computer: CPU, memory, input-output subsystems, control unit. Data representation: signed number representation, fixed and floating point representations, character representation. Computer arithmetic - integer addition and subtraction, ripple carry adder, carry look-ahead adder, etc. multiplication - shift-and-add, Booth multiplier, carry save multiplier, etc. Division - restoring and non-restoring techniques, floating point arithmetic.
Unit 1: Building blocks: Digital Logic System, Number Systems and Representation of Information
Unit 2: Computer Arithmetic and ALU
Unit 3: Structural and Functional view of Computer


Module 2: Addressing Modes, Instruction Set and Instruction Execution Flow (Week 2, 3 and 4)

Instruction set architecture of a CPU - registers, instruction execution cycle, RTL interpretation of instructions, addressing modes, instruction set. Case study - instruction sets of a generic CPU.
Unit 1: Component of Central Processing Unit (CPU) and External Interface
Unit 2: Main Memory
Unit 3: Instruction Execution
Unit 4: Instruction Format
Unit 5: Instruction Set
Unit 6: Addressing Modes-1
Unit 7: Addressing Modes-2
Unit 8: Flags and Conditional Instructions
Unit 9: Instruction: Procedure CALL/RETURN

Module 3: Hardware and Micro-program based control Unit Design (Week 5, 6 and 7)

CPU control unit design: hardwired and micro-programmed design approaches, Case study - design of a control unit of a simple hypothetical CPU.
Unit 1: Instruction Cycle and Micro-operations
Unit 2: Control Signals and Timing sequence
Unit 3: Control Signals for Complete
Instruction execution
Unit 4: Handling Different Addressing Modes
Unit 5: Handling Control Transfer Instructions
Unit 6: Design of Hard-wired Controlled Control Unit
Unit 7: Different Internal CPU bus Organization
Unit 8: Micro-instruction and
Micro-program Unit
9: Organization of Micro-programmed Controlled Control Unit

Module 4: Memory Architecture (Week 8, 9)

Memory system design: semiconductor memory technologies, memory organization: Memory interleaving, concept of hierarchical memory organization, cache memory, cache size vs. block size, mapping functions, replacement algorithms, and write policies.
Unit 1: Binary Cell and Memory Unit
Unit 2: Memory Cell Construction
Unit 3: Memory Unit and Interfacing
Unit 4: Cache Memory
Unit 5: Mapping Functions Unit 6: Replacement Policy

Module 5: Peripherals and Input-Output (Week 10, 11)

Peripheral devices and their characteristics: Input-output subsystems, I/O transfers - program controlled, interrupt driven and DMA
Unit 1: Input-Output Primitives
Unit 2: I/O Instructions and Addressing of I/O devices
Unit 3: Programmed I/O
Unit 4: Interrupt Driven I/O
Unit 5: DMA Transfer Unit 6: Storage Devices

Module 6: Performance Enhancement of Processor (Week 12, 13)

Introduction to concepts focusing on enhancing performance of processors i.e., Advanced Architecture
Unit 1: Performance enhancement: Pipeline
Unit 2: Performance enhancement: Parallelism
Unit 3: Pipeline Strategy
Unit 4: Multi-Processor
Unit 5: Interconnection Networks
Unit 6: Cache Coherence

Taught by

Santosh Biswas, J K Deka and Arnab Sarkar

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