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This course is about the automatic generation of digital circuits from high-level descriptions. Modern electronic systems are specified in Hardware Description Languages and are converted automatically into digital circuits. We will introduce the VHDL Hardware Description Language, and follow it up with a discussion of the basics of synthesis topics including High-level Synthesis, FSM Synthesis, Retiming, and Logic Synthesis.


Week 1 : Course Outline and Introduction to VLSI Design Automation
Week 2 : Hardware Description Languages and VHDL
Week 3 : Specifying Behaviour and Structure in HDL
Week 4 : Introduction to High-level Synthesis
Week 5 : Compiler Transformations in High-level Synthesis
Week 6 : Scheduling
Week 7 : Register Allocation and Timing Issues
Week 8 : Finite State Machine Synthesis
Week 9 : The Retiming Problem
Week 10 : Introduction to Logic Synthesis and Binary Decision Diagrams
Week 11 : Two-level and Multi-level Logic Optimisation
Week 12 : Technology Mapping, Timing Analysis, and Physical Synthesis

Taught by

Preeti Ranjan Panda

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