About the Course:The course will introduce students to the topics of Digital CMOS VLSI subsystem design using design metrics of delay, power, and area in detail. The course focuses more on power estimation, and interconnect aware designs and discusses on few power benefits designs. Approximate computing datapath subsystem designs will be analyzed along with the design, and error metrics. Different forms of standard cell design of latch, and flipflops will be discussed and the importance of timing parameters in sequential circuits will explained.INTENDED AUDIENCE: Students interested in Digital VLSIPREREQUISITES: Digital Electronics at Undergraduate level.INDUSTRY SUPPORT: Samsung, Intel, Broadcom, Qualcomm, IBM
Design and Analysis of VLSI Subsystems
NPTEL and Indian Institute of Information Technology, Bangalore via Swayam
This course may be unavailable.
Overview
Syllabus
Week 1: CMOS Transistors and Current model
Week 2: CMOS Inverter and characteristics
Week 3: Noise Margin and Delay of Inverter
Week 4: RC Delay
Week 5: Delay optimization
Week 6: Combinatorial Circuit Family
Week 7: Stick Diagram & Interconnects
Week 8: Interconnects (Contd)
Week 9: Power
Week 10: Static Power, and CMOS Latch and flipflop design
Week 11: Static Timing Analysis
Week 12: Adder subsystem design, and Approximate Computing
Taught by
Prof. Madhav Rao
