ABOUT THE COURSE: The course covers all the steps of VLSI Physical design flow needed for VLSI chip design. It includes all the steps of VLSI Physical design such as partitioning, chip planning, placement, Routing, and finally Clock routing. As the timing of digital circuits is important, two weeks will be completely dedicated to Static Timing Analysis (STA). The use of machine learning algorithms for VLSI Physical design will be explained. A demo of several Open-source tools such as Yosys, graywolf, qrouter, magic, OpenTimer, and OpenSTA is also included in the course.INTENDED AUDIENCE: BTech (ECE/EE) (4th year), MTech (Micro-electronics and VLSI), Ph.D. (ECE), and Ph.D. (CSE) students.PREREQUISITES: The digital design course is a pre-requisite for this course.INDUSTRY SUPPORT: All VLSI industries, For example: Intel, AMD, TI, Qualcomm, Analog Devices, ST-micro-electronics and many more.
VLSI Physical Design with Timing Analysis
Indian Institute of Technology Roorkee and NPTEL via Swayam
This course may be unavailable.
Overview
Syllabus
Week 1: Introduction to VLSI Physical Design
Lec-1: Introduction
Lec-2: Physical Design flow
Lec-3: Physical Verification
Lec-4: EDA Tools for Physical Design
Lec-5: Data Structures and Algorithms for Physical Design
Week 2:Static Timing Analysis – 1
Lec-6: Introduction (STA, DTA, Behaviour of synchronous circuit
Lec-7: Timing Arcs and Unateness
Lec-8: Definitions – Setup, Hold, Latch, Flipflop
Lec-9: STA (Flipflop)
Lec-10: STA (Flipflop)
Lec-11: STA (Latch)
Week 3:Static Timing Analysis – 2
Lec-12: STA (Latch)
Lec-13: Time Borrowing and Time Stealing - 1
Lec-14: Time Borrowing and Time Stealing - 2
Lec-15: OCV and CRPR
Lec-16: Multi-Mode Multi corner Analysis
Lec-17: Statistical Static Timing Analysis
Week 4:Partitioning
Lec-18: Introduction and Optimization goals
Lec-19: KL – Algorithm
Lec-20: Extensions of KL – Algorithm
Lec-21: FM - Algorithm
Lec-22: Multilevel Partitioning
Week 5:Chip Planning
Lec-23: Introduction and Optimization goals
Lec-24: Floorplanning Representations
Lec-25: Floorplanning Algorithms – 1
Lec-26: Floorplanning Algorithms - 2
Lec-27: Pin Assignment
Week 6:Placement
Lec-28: Introduction and Optimization goals
Lec-29: Min-cut placement
Lec-30: Analytic Placement
Lec-31: Simulated Annealing
Lec-32: Modern Placement Algorithms
Week 7:Routing – Global and Detailed
Lec-33: Introduction and optimization goals
Lec-34: Single net routing (Rectilinear routing)
Lec-35: Global routing in the connectivity graph
Lec-36: Finding shortest paths with Dijkstra’s Algorithm
Lec-37: Horizontal and vertical constraint graphs
Week 8:Routing – Global and Detaile
Lec-38: Channel Routing Algorithms
Lec-39: Switch box routing algorithms
Lec-40: Over the cell routing algorithms
Lec-41: Power and Ground routing
Lec-42: Unified Power Format and Special cells used for Power Planning
Week 9:Clock Routing
Lec-43: Clocking Schemes and Design Considerations
Lec-44: Clock Routing algorithms – 1 (H-tree based and MMM algorithms)
Lec-45: Clock Routing algorithms – 2 (Geometric matching and Weighted center algorithms)
Lec-46: Clock Routing algorithms – 3 (Exact zero skew and DME algorithm)
Lec-47: Skew, Latency, Uncertainty, and Jitter
Week 10:Input Files for VLSI Physical Design flow
Lec-48: Input Files: Physical Library, Technology Library (LEF), Standard Cell Technology Library (LEF)
Lec -49: Logical Library of Standard Cells: Operating Conditions, NLDM/ECSM models, Timing Desing Rule Constraints
Lec-50: Timing Desing Rule Constraints, Transition Table, Delay Table, Power Table
Lec-51: Parasitic Extraction, Wire Load Models, and RC table
Week 11:Machine Learning for Physical Design
Lec-52: Machine Learning Models
Lec-53: Predict Path-Based Slack from Graph-Based Timing Analysis
Lec-54: Data collection.
Lec-55: Model creation and predicting data
Week 12:Open-source VLSI Physical Design flow
Lec-56: Yosys - RTL Synthesis
Lec-57: graywolf - Placement
Lec-58: qrouter - Detailed routing
Lec-59: magic - VLSI Layout tool
Lec-60: OpenTimer and OpenSTA - Static timing analysis too
Lec-1: Introduction
Lec-2: Physical Design flow
Lec-3: Physical Verification
Lec-4: EDA Tools for Physical Design
Lec-5: Data Structures and Algorithms for Physical Design
Week 2:Static Timing Analysis – 1
Lec-6: Introduction (STA, DTA, Behaviour of synchronous circuit
Lec-7: Timing Arcs and Unateness
Lec-8: Definitions – Setup, Hold, Latch, Flipflop
Lec-9: STA (Flipflop)
Lec-10: STA (Flipflop)
Lec-11: STA (Latch)
Week 3:Static Timing Analysis – 2
Lec-12: STA (Latch)
Lec-13: Time Borrowing and Time Stealing - 1
Lec-14: Time Borrowing and Time Stealing - 2
Lec-15: OCV and CRPR
Lec-16: Multi-Mode Multi corner Analysis
Lec-17: Statistical Static Timing Analysis
Week 4:Partitioning
Lec-18: Introduction and Optimization goals
Lec-19: KL – Algorithm
Lec-20: Extensions of KL – Algorithm
Lec-21: FM - Algorithm
Lec-22: Multilevel Partitioning
Week 5:Chip Planning
Lec-23: Introduction and Optimization goals
Lec-24: Floorplanning Representations
Lec-25: Floorplanning Algorithms – 1
Lec-26: Floorplanning Algorithms - 2
Lec-27: Pin Assignment
Week 6:Placement
Lec-28: Introduction and Optimization goals
Lec-29: Min-cut placement
Lec-30: Analytic Placement
Lec-31: Simulated Annealing
Lec-32: Modern Placement Algorithms
Week 7:Routing – Global and Detailed
Lec-33: Introduction and optimization goals
Lec-34: Single net routing (Rectilinear routing)
Lec-35: Global routing in the connectivity graph
Lec-36: Finding shortest paths with Dijkstra’s Algorithm
Lec-37: Horizontal and vertical constraint graphs
Week 8:Routing – Global and Detaile
Lec-38: Channel Routing Algorithms
Lec-39: Switch box routing algorithms
Lec-40: Over the cell routing algorithms
Lec-41: Power and Ground routing
Lec-42: Unified Power Format and Special cells used for Power Planning
Week 9:Clock Routing
Lec-43: Clocking Schemes and Design Considerations
Lec-44: Clock Routing algorithms – 1 (H-tree based and MMM algorithms)
Lec-45: Clock Routing algorithms – 2 (Geometric matching and Weighted center algorithms)
Lec-46: Clock Routing algorithms – 3 (Exact zero skew and DME algorithm)
Lec-47: Skew, Latency, Uncertainty, and Jitter
Week 10:Input Files for VLSI Physical Design flow
Lec-48: Input Files: Physical Library, Technology Library (LEF), Standard Cell Technology Library (LEF)
Lec -49: Logical Library of Standard Cells: Operating Conditions, NLDM/ECSM models, Timing Desing Rule Constraints
Lec-50: Timing Desing Rule Constraints, Transition Table, Delay Table, Power Table
Lec-51: Parasitic Extraction, Wire Load Models, and RC table
Week 11:Machine Learning for Physical Design
Lec-52: Machine Learning Models
Lec-53: Predict Path-Based Slack from Graph-Based Timing Analysis
Lec-54: Data collection.
Lec-55: Model creation and predicting data
Week 12:Open-source VLSI Physical Design flow
Lec-56: Yosys - RTL Synthesis
Lec-57: graywolf - Placement
Lec-58: qrouter - Detailed routing
Lec-59: magic - VLSI Layout tool
Lec-60: OpenTimer and OpenSTA - Static timing analysis too
Taught by
Prof. Bishnu Prasad Das
