This course aims to educate learners on the benefits of using the RISC-V Instruction Set Architecture (ISA) and advocates for freely available ISAs. The course covers topics such as the background of RISC-V, its extensions, privileged architecture, hardware abstraction layer, and comparisons with other processors like ARM Cortex A5. The teaching method includes lectures on various RISC-V concepts, including atomic operations, compressed instructions, and supervisor architectures. The intended audience for this course is individuals interested in computer architecture, processor design, and open-source technologies.
Stanford Seminar - Instruction Sets Should Be Free- The Case for RISC-V
Stanford University via YouTube
Overview
Syllabus
Introduction.
My first computer.
ASPIRE Acorn Atom Shipped with Schematics.
Benefits from Viable Freely Open ISA.
What Style of ISA?.
RISC-V Background.
ASPIRE RISC-V is NOT an Open-Source Processor.
ASPIRE RISC-V Base Plus Standard Extensions.
"A": Atomic Operations Extension.
Variable-Length Encoding.
ASPIRE "C": Compressed Instruction Extension.
RISC-V Privileged Architecture.
RISC-V Hardware Abstraction Layer.
Four Supervisor Architectures.
Scala Embedded Language.
EOS Chip Roadmap in IBM 45nm SOI (design/fabrication funded by DARPA PERFECT/POEM).
Resilient Architecture with Vector-thread Execution.
ASPIRE "Rocket" Core Alpha Release, Oct 7, 2014.
ARM Cortex A5 vs. RISC-V Rocket.
RISC-V External Users.
ASPIRE Sponsors.
Taught by
Stanford Online
